MaxLinear Quad-Channel UART 68-Pin PLCC, ST16C554DCJ68-F

RS Stock No.: 170-4449Brand: MaxLinearManufacturers Part No.: ST16C554DCJ68-F
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Technical documents

Specifications

Brand

MaxLinear

Number of Channels per Chip

4

Transmit FIFO

16B

Receive FIFO

16B

Maximum Data Rate

1.5Mbit/s

Transmitter and Receiver FIFO Counter

Yes

Mounting Type

Surface Mount

Package Type

PLCC

Pin Count

68

Typical Operating Supply Voltage

2.97 → 5.5 V

Dimensions

24.33 x 24.33 x 3.68mm

Minimum Operating Temperature

0 °C

Maximum Operating Temperature

+70 °C

Country of Origin

Malaysia

Product details

Universal Asynchronous Receiver/Transmitter (UART), EXAR

Exar offer a variety of UARTs (Universal Asynchronous Receiver Transmitter) with a broad range of first in, first out (FIFO) depths, while supporting popular central processing unit (CPU) bus interface such as 8-bit VLIO.

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Please check again later.

Stock information temporarily unavailable.

P.O.A.

MaxLinear Quad-Channel UART 68-Pin PLCC, ST16C554DCJ68-F

19

Available in multiples of 19
19P.O.A.
38P.O.A.
57P.O.A.
76P.O.A.
95P.O.A.
114P.O.A.
133P.O.A.
152P.O.A.
171P.O.A.
190P.O.A.
209P.O.A.
228P.O.A.
247P.O.A.
266P.O.A.
285P.O.A.

P.O.A.

MaxLinear Quad-Channel UART 68-Pin PLCC, ST16C554DCJ68-F
Stock information temporarily unavailable.

19

Available in multiples of 19
19P.O.A.
38P.O.A.
57P.O.A.
76P.O.A.
95P.O.A.
114P.O.A.
133P.O.A.
152P.O.A.
171P.O.A.
190P.O.A.
209P.O.A.
228P.O.A.
247P.O.A.
266P.O.A.
285P.O.A.

Technical documents

Specifications

Brand

MaxLinear

Number of Channels per Chip

4

Transmit FIFO

16B

Receive FIFO

16B

Maximum Data Rate

1.5Mbit/s

Transmitter and Receiver FIFO Counter

Yes

Mounting Type

Surface Mount

Package Type

PLCC

Pin Count

68

Typical Operating Supply Voltage

2.97 → 5.5 V

Dimensions

24.33 x 24.33 x 3.68mm

Minimum Operating Temperature

0 °C

Maximum Operating Temperature

+70 °C

Country of Origin

Malaysia

Product details

Universal Asynchronous Receiver/Transmitter (UART), EXAR

Exar offer a variety of UARTs (Universal Asynchronous Receiver Transmitter) with a broad range of first in, first out (FIFO) depths, while supporting popular central processing unit (CPU) bus interface such as 8-bit VLIO.