Technical documents
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Product Type
Flip Flop IC
Input Type
Single Ended
Output Type
Differential
Polarity
Non-Inverting, Inverting
Mount Type
Surface Mount
Minimum Supply Voltage
1.65V
Package Type
SOIC
Pin Count
16
Maximum Supply Voltage
3.6V
Minimum Operating Temperature
-40°C
Trigger Type
Negative Edge
Flip-Flop Type
JK Type
Number of Elements per Chip
2
Maximum Operating Temperature
85°C
Height
1.58mm
Length
9.9mm
Width
3.91mm
Series
74LVC
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
Stock information temporarily unavailable.
P.O.A.
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P.O.A.
Stock information temporarily unavailable.
1
Technical documents
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Product Type
Flip Flop IC
Input Type
Single Ended
Output Type
Differential
Polarity
Non-Inverting, Inverting
Mount Type
Surface Mount
Minimum Supply Voltage
1.65V
Package Type
SOIC
Pin Count
16
Maximum Supply Voltage
3.6V
Minimum Operating Temperature
-40°C
Trigger Type
Negative Edge
Flip-Flop Type
JK Type
Number of Elements per Chip
2
Maximum Operating Temperature
85°C
Height
1.58mm
Length
9.9mm
Width
3.91mm
Series
74LVC
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
