Texas Instruments SN74LVC1G14DBVR Schmitt Trigger Inverter, 5-Pin SOT-23
Technical documents
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V, 5.5 ns @ 3.3 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Logic Family
LVC
Dimensions
2.9 x 1.6 x 1.15mm
Maximum Operating Supply Voltage
5.5 V
Height
1.15mm
Minimum Operating Supply Voltage
1.65 V
Width
1.6mm
Length
2.9mm
Maximum Operating Temperature
+85 °C
Minimum Operating Temperature
-40 °C
Propagation Delay Test Condition
50pF
Country of Origin
China
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
Stock information temporarily unavailable.
P.O.A.
25
P.O.A.
Stock information temporarily unavailable.
25
| quantity | Unit price |
|---|---|
| 25 - 100 | P.O.A. |
| 125 - 225 | P.O.A. |
| 250 - 475 | P.O.A. |
| 500+ | P.O.A. |
Technical documents
Specifications
Brand
Texas InstrumentsLogic Function
Inverter
Input Type
Schmitt Trigger
Number of Elements per Chip
1
Schmitt Trigger Input
Yes
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V, 5.5 ns @ 3.3 V
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Logic Family
LVC
Dimensions
2.9 x 1.6 x 1.15mm
Maximum Operating Supply Voltage
5.5 V
Height
1.15mm
Minimum Operating Supply Voltage
1.65 V
Width
1.6mm
Length
2.9mm
Maximum Operating Temperature
+85 °C
Minimum Operating Temperature
-40 °C
Propagation Delay Test Condition
50pF
Country of Origin
China
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22