Technical documents
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number of Channels
1
Schmitt Trigger Input
Yes
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V
Maximum Operating Supply Voltage
5.5 V
Dimensions
2.9 x 1.6 x 1.15mm
Height
1.15mm
Width
1.6mm
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2.9mm
Minimum Operating Temperature
-40 °C
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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P.O.A.
250
P.O.A.
250
Technical documents
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Schmitt Trigger Buffer
Number of Channels
1
Schmitt Trigger Input
Yes
Input Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOT-23
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
5 ns @ 5 V
Maximum Operating Supply Voltage
5.5 V
Dimensions
2.9 x 1.6 x 1.15mm
Height
1.15mm
Width
1.6mm
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2.9mm
Minimum Operating Temperature
-40 °C
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22