Texas Instruments SN74LVC1G32DCKR 2-Input OR Logic Gate, 5-Pin SC-70
Technical documents
Specifications
Brand
Texas InstrumentsLogic Function
OR
Mounting Type
Surface Mount
Number Of Elements
1
Number of Inputs per Gate
2
Schmitt Trigger Input
No
Package Type
SC-70
Pin Count
5
Logic Family
LVC
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-32mA
Maximum Propagation Delay Time @ Maximum CL
4 ns @ 5 V, 4.5 ns @ 3.3 V
Minimum Operating Supply Voltage
1.65 V
Maximum Low Level Output Current
32mA
Height
0.9mm
Width
1.25mm
Minimum Operating Temperature
-40 °C
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2mm
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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P.O.A.
3000
P.O.A.
3000
Technical documents
Specifications
Brand
Texas InstrumentsLogic Function
OR
Mounting Type
Surface Mount
Number Of Elements
1
Number of Inputs per Gate
2
Schmitt Trigger Input
No
Package Type
SC-70
Pin Count
5
Logic Family
LVC
Maximum Operating Supply Voltage
5.5 V
Maximum High Level Output Current
-32mA
Maximum Propagation Delay Time @ Maximum CL
4 ns @ 5 V, 4.5 ns @ 3.3 V
Minimum Operating Supply Voltage
1.65 V
Maximum Low Level Output Current
32mA
Height
0.9mm
Width
1.25mm
Minimum Operating Temperature
-40 °C
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
2mm
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family